The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for an ESD device incorporating a high voltage LDD structure for the manufacture of integrated circuits. The invention provides techniques for an ESD device which has a lower trigger voltage and offers more effective protection to the integrated circuit than conventional devices. Merely by way of example, the invention has been applied to ESD protection of high voltage I/O circuit for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is electrostatic discharge (ESD) protection devices used for the manufacture of integrated circuits in a cost effective and efficient way.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor Manufacturing International Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, in a high voltage process, it is difficult to fabricate efficient electrostatic discharge (ESD) bipolar junction transistor (BJT) devices. Because in a high voltage process deep N-type and P-type wells are used, conventional ESD bipolar devices built in these deep wells cannot be easily triggered by high voltage pulses caused by ESD events. Conventional high voltage ESD devices which include simple N+/P-well or P+/N-well diodes suffer from large areas and poor ESD performance.
FIG. 1 is a cross-sectional view diagram of a conventional bipolar ESD clamp device. As shown ESD clamp device 100 includes a bipolar transistor 140 formed with P-type double diffused drain (DDD) 130, high-voltage N-well 120, and P-type substrate 110. To provide device protection, an ESD bipolar transistor needs to trigger at a moderate voltage, for example 10-15 volts for some applications. Then a large current is allowed to flow through the bipolar transistor at a substantially reduced voltage, thus avoiding damages to other devices in the integrated circuit. In the conventional ESD clamp device shown in FIG. 1, the base width of bipolar transistor 140, which is determined by a depth of the HV N-well region 120 in FIG. 1, can be as large as 3 um. Therefore it would take a very high voltage for the bipolar transistor to trigger. As a result ESD protection is only provided by a diode junction breakdown in bipolar transistor 140. When operation voltage is higher than the junction breakdown voltage, for example, 30V, the energy of junction break down during the ESD pulse, which can be expressed as a product of voltage and current (V*I), can be very large. FIG. 2 is a simplified drawing of a current-voltage curve during a junction breakdown of a conventional bipolar ESD clamp device. Large devices are therefore needed to increase ESD junction area to avoid junction burnout. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.